HILRES'22 Summer School: Hardware in the Loop for Renewable systems with SoC platforms
Royal Holloway, University of London is organizing the first Summer School for young researchers, technically sponsored by ESoC Technical Committee of IES IEEE.
The event provides Master and PhD students, lecturer, researchers and engineers from academia and industry the opportunity to design/implement and hardware/software co-simulate a renewable energy system.
HILRES’22 aims to providing a three-day design from scratch experience of a bare-metal SoPC based Hardware in the Loop platform to model, simulate and control a complete Photovoltaic (PV) system using various design methodologies on low-cost SoC platforms.
HILRES'22 key activities:
Monday, 13th June 2022- Fundamentals of a photovoltaic system.
- Controlling a photovoltaic system.
- Matlab/Simulink modelling and simulation of a photovoltaic system.
- SoC & Zynq Architecture (heterogeneous SoC, Processor System, FPGA, architecture and interfacing)
- Designing with the Zynq (hardware design definition in Vivado using IP Integrator, custom IP, software development using Vitis and Petalinux).
- Core to Core Communication (synchronous and asynchronous communications, interface definition and selection, internal communication between different processor cores).
- SoC FPGA Hardware/software co-design of a photovoltaic system with PYNQ boards (Dual-core ARM Cortex-A9 processor, I/O, Timers, interrupts)
- VHDL fundamentals
- Co-simulation and FPGA in the Loop simulation of a MEPT controller.
- FPGA-based for Ac drive applications
- Hardware in the loop fundamentals
- SoC FPGA Hardware/software co-design of a photovoltaic system with PYNQ boards (D/A and A/D converters, PWM), Power converters on-chip modelling.
- Prof Mickael Hilairet, University of Bourgogne Franche-Comté, FR, (PV system modelling and control)
- Prof. Adam Taylor, Adiuvo Engineering and Training Ltd, UK (SoC design)
- Prof. Tarek Ould-Bachir, Polytechnique Montréal, CA (Power converters on-chip modelling)
- Dr Lahoucine Id-khajine, Cergy-Pontoise University, FR, (FPGA acceleration, Design tools)
- Dr Alin Tisan, Royal Holloway University of London, UK (SoC, VHDL design)
| Time | Event |
| 8 am - 8:45 am | Breakfast |
| 9am - 10:30am | HILRES session 1 |
| 10:30 - 11am | Coffee break |
| 11am - 12pm | HILRES session 2 |
| 12pm - 1pm | Lunch |
| 1:30 - 3pm | HILRES session 3 |
| 3pm - 3:30pm | Coffee break |
| 3:30pm - 5pm | HILRES session 4 |
| 7pm - 8:45pm | Dinner |
| Sunday, 7pm -8:45pm | Welcome dinner |
| Tuesday, 7pm - 9:30pm | Gala dinner |
- Access to the Summer School tutorials and Lab activities
- 3-day Full Board (accommodation and all meals included) at Royal Holloway, University of London Campus
- Coffee breaks, refreshments
- Gala dinner
- Note: the accommodation check-in is on the 12th of June and the check-out on the 15th of June
Further information
Booking essential. There will be only 20 tickets available, given on a first-come, first-served basis. Now, 10 tickets remaining!
